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fir.tar
FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)
- 2004-10-19 10:14:56下载
- 积分:1
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ASKMod
ASK调制信号的verilog VHL设计,在ise中实现了ASK信号的调制解调。(ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.)
- 2017-04-17 10:46:19下载
- 积分:1
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spwm
关于SPWM调制设计VHDL代码
关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)
- 2021-03-16 09:19:22下载
- 积分:1
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top-dac
Control with DAC conversion
- 2011-11-13 19:06:22下载
- 积分:1
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基于FPGA可触控卫星信道模拟器的设计与实现
说明: 卫星信道模拟器能够模拟卫星信道的传播特性,用于设备的通信调试,节
约研发成本。目前,很多卫星信道模拟器在参数设置上存在问题:有的参数难
以调节;有的采用上位机进行参数设置,通过上位机设置参数需要连接电脑,
适应性差。针对上述问题提出了一种基于FPGA可触控卫星信道模拟器,FPGA
作为算法实现和控制单元,通过控制触摸屏方便快捷的实现参数设置。(Literature of Satellite Channel Simulation Based on FPGA)
- 2020-12-10 20:59:20下载
- 积分:1
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Serial_Adder
注意:是verilog语言写的
一bit的全加器,实现4位数的串行加法器,一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)
- 2020-10-30 20:09:55下载
- 积分:1
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fir_vivado
此压缩包里面有基于vivado平台的工程,包括了正弦信号的产生,还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of
the generation of the signal of sin and the
design of fir filter and the ari)
- 2016-09-18 15:00:22下载
- 积分:1
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基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考...
基于FPGA的神经网络硬件实现中的关键问题研究,适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works
- 2022-04-17 01:07:47下载
- 积分:1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分:1
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rtl
SPI verilog RTL code
- 2016-02-29 12:26:08下载
- 积分:1