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BaseLine1
this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal
- 2012-12-12 00:58:21下载
- 积分：1
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fifo
fifo是大多数设计中非常重要的模块；
- 2022-02-27 06:51:03下载
- 积分：1
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qianzhaowang
说明： 一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)
- 2019-01-21 17:18:13下载
- 积分：1
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arp_2
rgmii接口通讯方式，用于FPGA以太网口开发(Rgmii interface communication mode)
- 2018-11-09 21:56:27下载
- 积分：1
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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
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PWM_LED
基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门(Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry)
- 2014-07-21 11:48:06下载
- 积分：1
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h.264解码器Verilog
本代码为h.264解码器的Verilog代码，在本压缩包中包含了全部Verilog代码，亲测成功，可以使用。
- 2023-07-28 17:35:03下载
- 积分：1
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LPC_Host
LPC host(By Lattice)
- 2017-07-13 11:00:01下载
- 积分：1
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CORDIC_ATAN
使用verilog语言完成了基于cordic算法求反正切的计算，精度为8次迭代(Verilog language used to complete based on CORDIC algorithm for arctangent calculation, an accuracy of 8 iterations)
- 2008-12-24 11:31:00下载
- 积分：1
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eetop.cn_16bits_multiplier
16位并行乘法器源代码，booth2编码，二进制树拓扑结构(16bits parallel multiplier source code
)
- 2020-12-24 20:59:05下载
- 积分：1
