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ffirr_166i
fir低通滤波器 用于dspbuilder pll:25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分:1
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Frame-synchronization
FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization
FPGA)
- 2011-06-21 10:41:22下载
- 积分:1
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自动售货机的VHDL程序与仿真VHDL源代码
自动售货机VHDL程序与仿真的vhdl的源代码-Vending machine VHDL procedures and simulation of vhdl source code
- 2022-04-12 03:18:12下载
- 积分:1
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float_int
自己编写的,浮点数与整数之间的转换的Verilog HDL实现(Written by myself, it is converted into Verilog HDL integer floating point implementation)
- 2020-12-18 10:29:11下载
- 积分:1
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BNN-PYNQ-master
在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)
- 2018-01-15 11:34:33下载
- 积分:1
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Snacke
基于NiosII系统的可以在DE2-115板子上运行的吞食蛇游戏!(可以使用RS2键盘进行控制)(DE2-115 board NiosII system swallowed snake game! , (RS2 keyboard control))
- 2013-01-01 10:12:03下载
- 积分:1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分:1
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FPGA中嵌入8051的核 并且实现控制128*64的液晶显示
FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD
- 2023-05-15 17:55:03下载
- 积分:1
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用VHDL语言编写的实现8位数据的并串转换,可下载在FPGA中
用VHDL语言编写的实现8位数据的并串转换,可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
- 2022-04-15 10:43:06下载
- 积分:1
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axi_master
自己写的 AXI master code(AXI master code)
- 2014-10-20 15:53:41下载
- 积分:1