-
wola
WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)
- 2020-09-28 14:57:45下载
- 积分：1
-
基于FPGA的技术溢出研究程序，只是一个测试程序，大家可以下着用一下。...
基于FPGA的技术溢出研究程序，只是一个测试程序，大家可以下着用一下。-FPGA-based research process of technology spillovers is only a test procedure, we can next look forward to using.
- 2023-04-25 10:30:03下载
- 积分：1
-
integer_chao_fpga
通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)
- 2021-02-20 22:49:43下载
- 积分：1
-
FPGA development board to write the Verilog code: function is from the client co...
FPGA开发板上写的Verilog代码：
功能是从电脑端发送一个字节，然后把它接收回来。
-FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
- 2022-03-17 03:39:34下载
- 积分：1
-
MATLAB产生单脉冲信号的数据 exp_rom
说明： 通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分：1
-
pdf
说明： 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA，包
括：步骤一、计算重构矩阵；步骤二、重构方位向
多通道数据，包括：步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零，并进行方位向傅里
叶变换；步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分：1
-
Verilog--image-sample
基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分：1
-
full adder
说明： vhdl code for full adder
- 2020-06-30 22:46:55下载
- 积分：1
-
频率计介绍了用VHDL语言编写的频率计的程序，详细编写了如何测频，如何计数频率。...
频率计介绍了用VHDL语言编写的频率计的程序，详细编写了如何测频，如何计数频率。-Cymometer introduce VHDL language with the frequency of the procedure in detail how to prepare a frequency measurement, how to count the frequency.
- 2023-05-28 07:15:03下载
- 积分：1
-
uart_rx
uart接收模块
// 波特率：9600
// 数据位：8
// 停止位：1
// 校验位：0(UART receive module
Baud rate: 9600 /
/ / data: 8
/ / stop: 1
/ / check digit: 0)
- 2017-07-10 13:56:54下载
- 积分：1
