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mini_cpu_verilog
用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)
- 2011-07-16 09:20:27下载
- 积分：1
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LIP4210CORE_SDIO
SDIO Verilog Sourcw code
- 2021-04-29 12:58:43下载
- 积分：1
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VGA_1
VGA显示原理与VGA时序实现论文,详细介绍了VGA的原理
(Principle and VGA VGA display timing to achieve paper, detailing the principles VGA)
- 2021-04-27 17:58:44下载
- 积分：1
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PA3_E_FROM_AN
actel flash rom使用 actel flash rom使用(actel flash rom actel flash rom)
- 2013-05-07 14:42:44下载
- 积分：1
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SVPWM_FPGA_ContainSourceCode
广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)
- 2013-12-30 16:00:11下载
- 积分：1
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gtx_aurora_zc706_example
Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
- 2018-01-23 08:53:37下载
- 积分：1
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ADPCM(1)
adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)
- 2013-04-17 17:07:54下载
- 积分：1
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FPGA开发全攻略
FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分：1
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S05_example_Network
vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
