登录
首页 » VHDL » 用状态机实现一序列检测器,即检测到串行码{1110010}后,检测器输出1,否则输出0;...

用状态机实现一序列检测器,即检测到串行码{1110010}后,检测器输出1,否则输出0;...

于 2022-02-05 发布 文件大小:46.51 kB
0 171
下载积分: 2 下载次数: 1

代码说明:

用状态机实现一序列检测器,即检测到串行码{1110010}后,检测器输出1,否则输出0; -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • zidongshouhuoji
    使用VHDL语言实现的一个自动售货机的程序。适合VHDL初学者使用。(VHDL language using a vending machine program. VHDL suitable for beginners.)
    2011-04-29 21:28:00下载
    积分:1
  • PID_Verilog
    说明:  之前一直找不到自学编写了一个,PID案例,分享下(I have been unable to find a self-taught, compiled a PID case, share under)
    2020-10-08 13:26:54下载
    积分:1
  • 8aqm-string-and-convert-vhdl-program
    8aqm调制串并转(1:3)换部分vhdl程序(8aqm string and convert vhdl program)
    2011-01-20 18:31:26下载
    积分:1
  • 在nexys2数字cronometer
    该项目是用VHDL编写的,并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止,在按钮0中复位。显示方式与显示方式不同最小:分段到hr:min通过切换开关1
    2022-11-12 07:55:03下载
    积分:1
  • LCD1602-TEST
    利用verilog驱动LCD1602 本实验是用LCD1602显示英文。(LCD带字库)(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))
    2013-12-16 13:51:35下载
    积分:1
  • vhdl_codes
    D-flip flop vhdl implement code
    2012-04-13 14:03:13下载
    积分:1
  • gtx_aurora_zc706_example
    Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议,通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式,以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
    2018-01-23 08:53:37下载
    积分:1
  • LEDtest
    vhdl 实现fpga 闪灯控制 流水线闪灯 还用signalTAP进行检测,给初学者参考(vhdl fpga flash control lines to achieve flash is also used signalTAP testing, to advanced users)
    2010-06-10 16:27:57下载
    积分:1
  • JTAG_Example0_Verilog
    一个Verilog的JTAG程序例子,包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
    2021-04-27 13:48:44下载
    积分:1
  • LIP4210CORE_SDIO
    SDIO Verilog Sourcw code
    2021-04-29 12:58:43下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载