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Turbo Decoder Release 0.3
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
-Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output
Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL
model
- 2022-01-30 12:47:05下载
- 积分：1
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06042349
Dynamic Power Management for the Iterative Decoding of Turbo Codes
- 2014-04-04 15:03:28下载
- 积分：1
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yinpin_display0925
实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)
- 2016-01-07 10:08:31下载
- 积分：1
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taxione
说明： 基于VHDL出租车的设计，实现开动、停止的收费功能。(VHDL-based cab design, implementation and running, stop the charging function.)
- 2010-04-25 14:33:58下载
- 积分：1
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this a spartan 3E base project file.
this is the project of game in which vga...
this a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.-this is a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.
- 2023-07-29 01:40:03下载
- 积分：1
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Quartus II TimeQuest时序分析器说明书
说明： Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
- 2020-08-07 17:48:31下载
- 积分：1
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一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！
一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！-A simple shift register. VHDL language, and perhaps will help you!
- 2023-07-05 13:15:03下载
- 积分：1
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cycle_measure
测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)
- 2013-08-29 16:09:17下载
- 积分：1
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用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS
用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
- 2022-03-24 12:46:20下载
- 积分：1
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大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持...
大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
- 2022-11-25 02:20:03下载
- 积分：1
