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sd_slave_device
verilog source code for SD card SLAVE DEVICE IP-Core
- 2021-04-12 22:18:56下载
- 积分:1
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DDC_Ver1.0
数字下变频(DDC)在如今基于软件无线电的架构中对系统的整体性能决定性的影响,代码为基于Matlab的4通道DDC程序,程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
- 2010-08-04 18:33:14下载
- 积分:1
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BPSK
说明: 先用Matlab理论仿真,再用Verilog语言在ISE环境下编写程序,可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)
- 2020-06-19 22:40:02下载
- 积分:1
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移位乘法器的输入为两个4位操作数a和b,启动乘法器由stb控制,clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1....
移位乘法器的输入为两个4位操作数a和b,启动乘法器由stb控制,clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1.
乘法算法采用原码移位乘法,即对两个操作数进行逐位的移位相加,迭代4次后输出结果。具体算法:
1. 被乘数和乘数的高位补0,扩展成8位。
2. 乘法依次向右移位,并检查其最低位,如果为1,则将被乘数和部分和相加,然后将被乘数向左移位;如果为0,则仅仅将被乘数向左移位。移位时,被乘数的低端和乘数的高端均移入0.
3. 当乘数变成全0后,乘法结束。
-err
- 2022-04-10 04:29:26下载
- 积分:1
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adder16b
说明: 潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)
- 2009-07-23 17:02:22下载
- 积分:1
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STM32与FPGA通信
stm32与fpga之间的通信,协议是SPI的,可双向通信(双向通信需要自己例化,只例化了fpga到stm32)(Communication between STM32 and FPGA, the protocol is SPI, two-way communication (two-way communication needs to be taken as an example, only FPGA to STM32))
- 2020-11-16 09:49:40下载
- 积分:1
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cic
cic设计 verilog verilog(cic verilog design verilog)
- 2012-10-23 20:13:52下载
- 积分:1
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一篇比较好的spi接口的vhdl实现的参考
一篇比较好的spi接口的vhdl实现的参考-A relatively good spi interface realize VHDL reference
- 2023-05-08 20:50:03下载
- 积分:1
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FPGA将从CY7C68013读到的数写入SRAM
FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM
- 2022-04-09 09:00:14下载
- 积分:1
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CAN--for-FPGA
FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错(FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA)
- 2011-04-19 18:51:12下载
- 积分:1