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ov7670_sdram_vga_sobel
基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。
FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board.
FPGA edge detection)
- 2019-04-23 17:31:00下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
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FPGA-Racing-Game
在开发板EGO1上实现赛车游戏,语言为verilog，内含bits文件(racing game in verilog)
- 2020-12-24 13:39:07下载
- 积分：1
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In the FPGA to achieve the sound card interface, flower, filter comparators, the...
在FPGA上实现声卡接口，电子琴，滤波比较器，最终实现语音通信
-In the FPGA to achieve the sound card interface, flower, filter comparators, the eventual realization of voice communications
- 2022-01-25 20:35:57下载
- 积分：1
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DMA
针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)
- 2009-07-04 23:14:32下载
- 积分：1
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fpgaspi
LabVIEW FPGA SPI implementation
- 2013-04-30 00:03:18下载
- 积分：1
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MIPSTOP
misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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IIC总线协议，VHDL语言编写，可以直接使用
IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly
- 2022-07-11 11:04:33下载
- 积分：1
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用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!
用VHDL语言实现的图像传感器TCD132D的时序驱动代码,时序精准!-VHDL language with the image sensor TCD132D realize the timing-driven code, timing accurate!
- 2022-01-26 02:25:08下载
- 积分：1
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DSP_INTERFACE
DSP与FPGA时序接口模块，已经经过测试，保证读写稳定(The Interface of DSP to FPGA)
- 2021-01-08 10:58:51下载
- 积分：1
