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xapp265
High-Speed Data Serialization and
Deserialization(840 Mb/s LVDS)
for xilinx fpga
- 2010-03-16 16:25:41下载
- 积分：1
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shuzi
讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form
)
- 2011-12-17 00:55:01下载
- 积分：1
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VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
- 2022-02-11 16:15:23下载
- 积分：1
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MAX2 EPLD 的测试程序, VHDL语言编写.
MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.
- 2022-01-26 06:18:20下载
- 积分：1
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frame_decode_and_encode
一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)
- 2006-07-12 15:10:07下载
- 积分：1
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VHDLexample
VHDL开发程序，有程序仿真的截图，方便验证调试结果。并有程序说明(VHDL 驴 陋 垄 鲁 脤臑貌 拢 卢 脫臑 鲁 脤臑貌 脗脮忙渭脛 陆 脴脥 录拢卢路陆卤 茫脩茅脰 陇 渭 梅 脢脭 陆 谩 鹿 没 隆 拢 虏 垄 脫臑 鲁 脤臑貌脣渭脙 梅)
- 2008-04-10 16:11:04下载
- 积分：1
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zw222
ZardWars Files
------------------------------
- 2014-03-20 01:43:16下载
- 积分：1
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using_memory_allocation_mger
vmm primer的使用使用文档，和之前vmm primer源代码配套使用！(vmm the primer use of the use of the document, and before supporting vmm the primer the source code to use!)
- 2012-12-23 22:43:30下载
- 积分：1
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veilog code user can derict use it for the base mode.
veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
- 2023-08-09 02:40:03下载
- 积分：1
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20190718
uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分：1
