登录
首页 » VHDL » PCI总线仲裁参考设计,Quicklogic提供的verilog代码

PCI总线仲裁参考设计,Quicklogic提供的verilog代码

于 2022-03-11 发布 文件大小:3.40 kB
0 154
下载积分: 2 下载次数: 1

代码说明:

PCI总线仲裁参考设计,Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • concurrent
    VHDL operators basics
    2013-09-10 14:44:51下载
    积分:1
  • Verilog LDPC码
    说明:  LDPC码的BP译码verliong程序(BP decoding veriong program of LDPC code)
    2020-03-03 18:14:12下载
    积分:1
  • Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL...
    _EDA实验讲义EDA实验指导书EDA技术与VHDL第3章EDA技术实用教程EAD技术与实践.等等资料-Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL in Chapter 3 of EDA technologies utility EAD Technology and Practice Guide. And so on Information
    2022-09-22 04:20:06下载
    积分:1
  • FPGA-DSP
    vhdl编写的FPGA与DSP接口程序,在FPGA内分配了两块双BUFFER与DSP进行通信(vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP)
    2021-01-08 10:58:51下载
    积分:1
  • generateCAcode
    gps C/A码生成 生成gps32颗卫星伪码,方便,经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)
    2021-05-13 04:30:02下载
    积分:1
  • 2FSK
    基于FPGA的2FSK调制解调,里面有详细的工程说明,对于学习ISE软件和通信原理的知识很有帮助(FPGA based 2FSK modulation and demodulation, which contains detailed engineering instructions, for learning ISE software and communication principles of knowledge is very helpful.)
    2018-06-30 17:49:20下载
    积分:1
  • tr_wave
    FPGA编写的三角波发生器,可以产生100HZ~500KHZ以上的三角波,波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)
    2007-08-25 03:15:38下载
    积分:1
  • AMBA
    AMBA总线规范,能对从事嵌入式的同行们有一些帮助,让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)
    2012-12-06 20:35:22下载
    积分:1
  • 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
    一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
    2022-08-21 18:15:23下载
    积分:1
  • USB_GPIF-II
    fpga模拟两路视频,简单拼接后,经过GPIF II接口传出给cy2014,测试usb的吞吐量(fpga generate two lane video, and transmit them through GPIF II interface. test cy2014)
    2017-06-02 18:50:04下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载