-
VGA count, PSW2 inverse control is counting? Reduced count, pop
VGA计数，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
- 2022-04-17 09:49:34下载
- 积分：1
-
verilog
lap of altera . it s basic about verilog
- 2010-06-25 20:30:32下载
- 积分：1
-
cmos-Digital-design
The deep lecture notes for basic digital system for cmos design
- 2012-07-29 17:51:26下载
- 积分：1
-
rtl_wangjiangxing
ecc椭圆算法RTL,verilog源代码经过验证，用于FPGA或者ASIC(ECC elliptic curve encryption algorithm for Verilog implementation)
- 2015-01-29 18:43:47下载
- 积分：1
-
e2
Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
-
water_light
Verilog语言的流水灯设计程序，对初学者很有用。(Water lights Verilog language design program useful for beginners.)
- 2015-03-15 13:48:43下载
- 积分：1
-
dac9747
主要完成ADI公司的DAC（数字-模拟转换器）AD9747的SPI接口及寄存器配置(Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of)
- 2014-06-03 11:00:43下载
- 积分：1
-
8 位加法器
有一个 8 位全加器 VHDL 代码。我测试该代码在协同，看到了这段代码的工作。
- 2022-04-21 11:16:03下载
- 积分：1
-
课程设计-数字钟
说明： 具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)
- 2020-05-18 17:11:07下载
- 积分：1
-
loop
对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)
- 2008-12-17 23:00:35下载
- 积分：1
