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Core1553BRT_EBR_EV_20
actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)
- 2021-05-06 18:58:37下载
- 积分：1
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基于VHDL的LED显示控制程序
常用的VHDL语言编写的LED灯控制程序,这是教学用的，开发板采用的是EPM240T100C5N，买开发板时附带的程序
- 2022-05-19 04:48:48下载
- 积分：1
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Hardware-CNN-master
说明： Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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Practical-Statecharts-in-C-and-CPP
QP编程创始人所著的介绍QP编程思想的书，中文版。QP是用于嵌入式中状态机编程的开源软件。(QP programming book written by the founder of the introduction of QP programming ideas, and Chinese version. QP is open source software for embedded state machine programming.)
- 2015-03-07 18:00:15下载
- 积分：1
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Wishbone dma ip core
Wishbone dma ip core
- 2022-01-26 04:18:15下载
- 积分：1
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PCI-based--DSG
基于PCI的数字信号发生器
关键词：PCI总线，PCI9054，FPGA，卡尔曼滤波器(PCI-based digital signal generator
Keywords: PCI bus, PCI9054, FPGA, Kalman filter)
- 2016-06-12 20:41:45下载
- 积分：1
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设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。...
设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
- 2022-02-04 07:33:00下载
- 积分：1
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这是用VHDL实现的8位加法器，对新手有点帮助。
这是用VHDL实现的8位加法器，对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.
- 2022-07-20 21:54:41下载
- 积分：1
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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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adc0809
1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果；
2、设置有复位和启动/保持开关，要求
⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备；
⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。
3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)
- 2021-01-02 21:38:57下载
- 积分：1
