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This is an 16 bit adder using vhdl
实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl
- 2023-09-07 11:05:03下载
- 积分：1
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AMI1
本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)
- 2021-04-22 14:48:48下载
- 积分：1
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16QAM
说明： 在quartus上运行16QAM仿真，实现在modelsim上的波形仿真(Running 16QAM simulation on quartus)
- 2020-04-27 18:24:11下载
- 积分：1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
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Get-20-point
this program get 20 point from user and draw functions.
- 2014-01-09 03:25:06下载
- 积分：1
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Digital signal source, the output of different frequency, phase is the cosine si...
数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,
- 2022-04-23 09:40:37下载
- 积分：1
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vga
VGA显示控制：时序控制+像素点的颜色处理显示十字光标（vorilog）(VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog))
- 2010-11-27 14:02:12下载
- 积分：1
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ethernet_tri_mode_rtl.tar
以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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一个视频信号输入的verilog源代码，里面含有相关的使用文档。...
一个视频信号输入的verilog源代码，里面含有相关的使用文档。-A video signal input of the Verilog source code, which contains documents related to the use.
- 2023-02-03 13:40:04下载
- 积分：1
