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给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)
- 2017-04-05 13:50:53下载
- 积分：1
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32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考...
32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
- 2023-09-04 17:30:04下载
- 积分：1
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一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考...
一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
- 2022-01-31 04:35:55下载
- 积分：1
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Vending-Machine-using-Moore
Vending Machine simulation using Moore sequence
- 2016-05-30 08:24:35下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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通过VGA接口获取视频输出的VHDL代码
vhdl code for obtaining video output through vga port
- 2022-02-04 13:35:30下载
- 积分：1
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verilogsram
SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)
- 2017-04-20 22:20:05下载
- 积分：1
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FPGA将从CY7C68013读到的数写入SRAM
FPGA将从CY7C68013读到的数写入SRAM-FPGA will read a few CY7C68013 write SRAM
- 2022-04-09 09:00:14下载
- 积分：1
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SDH接收处理
模拟SDH帧结构，设计了状态机，能从连续传输的SDH字节流中找出帧头；从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟；设计了输入信号，输出包括E2串行数据、E2串行时钟和SDH帧头位置指示
- 2023-07-26 18:40:02下载
- 积分：1
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StepperMotorDrivepinassign
stepper motor vhdl pin assignments and code
- 2011-08-12 23:15:46下载
- 积分：1
