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- 2022-01-26 03:14:33下载
- 积分：1
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8051参考设计，和其他免费知识产权在8051相比，相对整个D。
8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
- 2023-01-19 15:30:04下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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AXI4_Sim
说明： 实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)
- 2020-05-31 15:20:16下载
- 积分：1
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VHDL参考程序，他们的初学者参考使用
vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners
- 2022-04-19 08:23:59下载
- 积分：1
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rfid_re
VHDL实现 DDS。大家共享吧，一起学习，一起进步(VHDL realize DDS. U.S. to share it with learning, with progress)
- 2008-05-16 15:12:13下载
- 积分：1
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altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中...
altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II
- 2022-12-14 08:55:03下载
- 积分：1
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TCAM
基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示(TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions)
- 2014-12-10 20:41:31下载
- 积分：1
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clock_6
说明： ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
- 2020-06-24 12:00:02下载
- 积分：1
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8位CPU的VHDL设计代码没有测试
8 bit cpu vhdl design code not tested
- 2022-03-21 20:07:37下载
- 积分：1
