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CC
说明: 802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)
- 2015-05-14 23:05:54下载
- 积分:1
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基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计...
基于FPGA的快速傅立叶变换实现,适合fpga工程技术人员参考设计-FPGA-based Fast Fourier Transform for fpga reference design engineers
- 2022-12-10 15:50:11下载
- 积分:1
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135个经典VerilogHDL源码和说明文档,入门的好资料
135个经典VerilogHDL源码和说明文档,入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry
- 2022-01-20 23:10:53下载
- 积分:1
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OFDM_CP
ofdm系统的matlab实现,包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分:1
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内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity...
内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
- 2022-08-11 02:50:00下载
- 积分:1
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GgmsskModulatM
GMSK的调制解调,理理想信道,画出其功率谱。
(GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
- 2020-07-02 02:00:02下载
- 积分:1
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virtex7_pcie_dma
FPGA开发PCIe的源码,采用VHDL语言,通过此源码,能更好的掌握PCIe总线,使开发者少走弯路,
- 2023-01-25 04:55:04下载
- 积分:1
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UART(RS232)
用VERILOG语言实现的通用异步串行收发器(RS232收发器),波特率可设置,通讯稳定,已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)
- 2021-04-01 10:59:08下载
- 积分:1
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用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。...
用VHDL写的运动计时表程序,用Modelsim仿真已经通过,帖出来与大家分享。-write VHDL campaign time table program, Modelsim simulation has been passed, Tie up share with you.
- 2022-01-26 05:57:13下载
- 积分:1
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test bench for alu 6 functions
test bench for alu 6 functions
- 2022-03-02 06:50:51下载
- 积分:1