-
本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!
本程序使用vhdl编写的jtag接口实现程序,其中有些功能未能实现,希望有人能够帮忙完善!-vhdl the procedures used to prepare the jtag interface procedures, which some of them did not materialize, hope someone can help perfect!
- 2022-03-01 07:15:01下载
- 积分：1
-
Divider can be very good VHDL divider realize the function of great help for beg...
除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助.
-Divider can be very good VHDL divider realize the function of great help for beginners.
- 2022-04-21 12:12:32下载
- 积分：1
-
led1
点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分：1
-
agc
数字自动增益控制 AGC （automatic gain control） Verilog(automatic gain control Verilog)
- 2021-03-11 19:29:25下载
- 积分：1
-
final-delivery
Block LU decompostion of a matrix
- 2014-10-08 15:33:16下载
- 积分：1
-
AD9516VERILOG
通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)
- 2021-03-15 12:09:23下载
- 积分：1
-
canny
说明： canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)
- 2021-04-12 14:48:57下载
- 积分：1
-
rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分：1
-
decodeLogDomainSimple
When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.
- 2017-01-29 18:04:53下载
- 积分：1
-
Fpga_control
FPGA做机器人舵机控制系统，verilog(FPGA to do the robot servo control system, verilog)
- 2020-10-26 18:09:59下载
- 积分：1
