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timescale-1ns
说明： 这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)
- 2011-04-13 19:21:39下载
- 积分：1
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简易数字频率计
利用FPGA制作的简易数字频率计，简单实用。
- 2023-08-17 21:50:03下载
- 积分：1
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ds18b20_verilgo
艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)
- 2010-10-26 11:25:18下载
- 积分：1
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dma_ahb
挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。(Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.)
- 2021-03-29 21:49:10下载
- 积分：1
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PWM
通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分：1
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AHB2APB Bridge 的Verilog
在AMBA bus 总线中，AHB是高速的总线接口，APB则是低速的总线接口，有些低速的外设不需要接入高速的外设时，便通过桥接的方式接入APB总线中。
- 2022-01-20 22:42:04下载
- 积分：1
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lab6
说明： 使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)
- 2020-12-08 13:10:53下载
- 积分：1
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verilog-ethernet
说明： Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.
- 2021-04-17 23:38:52下载
- 积分：1
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i2c_master_bfm仿真模型
i2c_master_bfm，可以直接使用实现i2c master的仿真功能
- 2023-08-23 13:05:03下载
- 积分：1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分：1
