-
FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分:1
-
基于FPGA的交通控制器
设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器: 1) 主、支干道各设有3个方向的绿、黄、红指示灯(左转、直行和右转),每个行驶方向均配有时间显示数码管;2) 主干道处于常允许通行状态,而支干道有车来才允许通行(由外部信号通知)。3) 当主、支道均有车时,两者交替允许通行,主干道每次放行90s,支干道每次放行60s,在每次由亮绿灯变成亮红灯的转换过程中,要亮5s黄灯作为过渡,并进行减计时显示。
- 2022-02-26 08:00:04下载
- 积分:1
-
10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分:1
-
VHDL与源代码包
VHDL与源代码包-and VHDL source code
- 2022-02-03 22:44:25下载
- 积分:1
-
LEDTest2
This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing
- 2017-10-28 16:27:20下载
- 积分:1
-
McBSP
CPLD对mcbsp的收发操作,占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分:1
-
Cirrus Logic EP9302 原理图 ORCAD格式
Cirrus Logic EP9302 原理图 ORCAD格式-Cirrus Logic EP9302 schematic ORCAD format
- 2022-08-22 05:47:43下载
- 积分:1
-
alu3
用verilog语言编写,一个8-bit ALU,可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分:1
-
VHDL教学的经典之作,大家学习必看的书籍。
VHDL教学的经典之作,大家学习必看的书籍。-VHDL teaching classic, must-see U.S. study books.
- 2022-12-05 21:15:06下载
- 积分:1
-
picorv32-master
PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.
- 2020-06-24 21:40:01下载
- 积分:1