-
exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
-
an example HDL
an example HDL-Core with any basic gates.
- 2022-12-05 05:05:03下载
- 积分：1
-
rtl
基于脉动结构的有限域乘法器，verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)
- 2010-01-04 11:48:50下载
- 积分：1
-
for Dictyophora board, in the way of achieving LCD clock function.
适合DE2板，能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.
- 2023-08-10 07:45:03下载
- 积分：1
-
SYSTEMVIEWQPSK
使用 System view 编程 QPSK(use System Programming view QPSK)
- 2021-01-04 21:38:54下载
- 积分：1
-
e2
说明： Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency
- 2014-02-23 02:42:47下载
- 积分：1
-
verilog
数字信号除了的FPGA实现的Verilog源代码，之前发过一份是VHDL，各有所需吧，需要的看看吧(Digital signal in addition to the realization of the FPGA Verilog source code, send before a is VHDL, each have need it, need to look at it
)
- 2012-02-25 15:06:35下载
- 积分：1
-
verilog-PS2
说明： 在FPGA内，实现PS2键盘数据读取功能，verilog源代码(In the FPGA, achieving PS2 keyboard data read functions, verilog source code)
- 2009-08-28 16:10:24下载
- 积分：1
-
11880608svpwm
正弦波电流驱动的无刷直流电机性能分析，通过分析方波电流驱动与正弦波电流比较，得出正弦波电流驱动电机性能较好(Sine wave current drive brushless DC motor performance analysis, by analyzing the square-wave current drive with sine wave current comparison, the sine-wave current drive motor performance is better)
- 2013-06-17 11:16:46下载
- 积分：1
-
verilog时钟分频器~ 50hmz波特率9600bps，使用~
verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分：1
