-
test-bench
如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)
- 2012-03-31 08:38:24下载
- 积分：1
-
VHDLexamples
这里面有很多的vhdl的编程的源代码，文件是全英文的，例子丰富(That there are a lot of vhdl programming source code, documentation is in English, and examples of rich)
- 2010-07-13 11:00:53下载
- 积分：1
-
VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分：1
-
8051core
8051core-Verilog FPGA的51单片机内核源代码!
-8051core-Verilog FPGA 51 Singlechip kernel source code!
- 2023-02-06 02:20:03下载
- 积分：1
-
BIT
说明： FPGA应用状态机版，适合初学者学习状态机三段式，ASMD图的理解和翻译，以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述
根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description
According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)
- 2020-04-28 15:57:34下载
- 积分：1
-
sep_fram_v0.0
直接序列扩频系统的收发系统，可以进行参数配置(this is a Verilog program )
- 2016-03-01 13:22:03下载
- 积分：1
-
UART
实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分：1
-
I2C控制器源代码，Verilog HDL语言，可以直接调用
I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
- 2023-04-28 04:45:03下载
- 积分：1
-
clk_div3
在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分：1
-
clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分：1
