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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分：1
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Exercise4
AES TSAPI Retrieve Event in Non-blocking Mode
- 2019-05-07 20:04:58下载
- 积分：1
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unishift
An universal shift register performs the following tasks load, right shift ,left shift and parallel load as the selection inputs are 00,01,10,11 respectively. Such a register is implemented here in Quartus.
- 2009-09-24 18:56:48下载
- 积分：1
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prbs编码FPGA实现
PRBS的验证就是PRBS的产生的反过程，具体方法是Transceiver接收端首先将收到的数据寄存一拍（并行 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报
- 2022-07-20 20:27:10下载
- 积分：1
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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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Xilinx vivado authoritative course
Xilinx vivado 权威教程，清华大学出版社出版，何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
- 2019-02-19 20:37:09下载
- 积分：1
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6
说明： 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。
设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。
输入：连续脉冲，逻辑开关；输出：七段LED。
(4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously.
Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output.
Input: Continuous pulse, logic switches output: seven-segment LED.)
- 2010-06-21 22:07:59下载
- 积分：1
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PID controller verilog源代码
The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).
- 2022-09-23 12:05:03下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
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halfband
verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)
- 2020-12-25 14:29:04下载
- 积分：1
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