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my_booth_mp
booth algotihm verilog design and test
- 2016-06-14 16:02:10下载
- 积分：1
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liuy
一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)
- 2010-08-25 12:26:25下载
- 积分：1
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izhihuangenzongPWMnb
三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)
- 2012-11-26 11:56:56下载
- 积分：1
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基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有
基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有-The octave-based EDA player automatically have a flower design language VHDL design
- 2022-07-23 01:54:55下载
- 积分：1
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code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
- 2022-04-09 10:05:17下载
- 积分：1
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fft
FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分：1
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该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。...
该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.
- 2022-01-24 17:35:43下载
- 积分：1
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NIOS设计从入门到精通
nios大神进阶，一本非常好的FPGA书籍，从RTL到eclips(nios tech.a very good book learning FPGA tech.)
- 2018-06-04 11:39:01下载
- 积分：1
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DE2_115_CAMERA
d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )
- 2020-07-09 20:38:55下载
- 积分：1
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SSI-ABZ
说明： SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)
- 2019-05-19 15:37:48下载
- 积分：1
