登录
首页 » VHDL » 设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源...

设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源...

于 2022-02-12 发布 文件大小:479.36 kB
0 39
下载积分: 2 下载次数: 1

代码说明:

设计并制作一个14键单音电子琴预先存入一些曲谱电路在4Hz的时钟控制下自动播放 通过220V电源适配器给电路提供工作电源-Design and production of a 14-key electric piano tone into a number of music scores advance in 4Hz clock circuit under the control of automatic play through 220V power adapter to provide power to the circuit

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • PWM_LED
    基于DE2_70平台,编写nios软核c代码,控制流水灯,硬件实现验证通过,适合入门(Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry)
    2014-07-21 11:48:06下载
    积分:1
  • 学习Xilinx公司开发软件ISE的基础资料,从最基础到复杂逻辑设计。
    学习Xilinx公司开发软件ISE的基础资料,从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.
    2022-05-27 10:26:09下载
    积分:1
  • VHDL digital system design and engineering practice 4, including the principles,...
    VHDL数字系统设计和工程实践5,包含原理,真值表和原理图,以及VHDL源代码.-VHDL digital system design and engineering practice 4, including the principles, truth table and schematic, as well as VHDL source code.
    2022-08-11 13:48:51下载
    积分:1
  • n_bit_counter
    n bit generic shift registers
    2011-03-18 17:55:19下载
    积分:1
  • SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。 ODD_110BREG是一个3位的备...
    SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。 ODD_110BREG是一个3位的备份寄存器,寄存器中存放的是奇数帧的同步头,也就是110。 EVEN_9BHREG是一个8位的备份寄存器,寄存器中存放的是偶数帧的同步头,也就是10011011。这两个寄存器的初始值在系统一开始就打入。 -SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
    2022-05-15 03:11:22下载
    积分:1
  • 层合板刚度
    层合板的刚度的计算和验算,包括拉伸刚度A、弯曲刚度D以及耦合刚度B。 首先要给定层合板的各个参数,具体有:层合板的层数N;各单层的弹性常数E1、E2、 、G12;各单层对应的厚度;各单层对应的主方向夹角 。(The stiffness of laminated plates is calculated and checked, including tensile stiffness, A, flexural stiffness, D and coupling stiffness B. First of all, it is necessary to give the parameters of laminated plates, such as the number of plies N, the elastic constants of each layer, E1, E2, and G12, the thickness of each monolayer, and the angle of the main direction corresponding to each single layer.)
    2021-01-18 09:28:43下载
    积分:1
  • 1_Carm
    说明:  经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
    2019-03-19 13:38:29下载
    积分:1
  • Chapter2
    通信IC设计的第二章Verilog参考学习代码,方便初学者学习入门,供学习参考用The codes of Chapter1 of《Communication IC Design》(The codes of Chapter2 of《Communication IC Design》)
    2017-03-07 15:47:04下载
    积分:1
  • Buffer-DAQ
    基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)
    2015-01-11 19:09:49下载
    积分:1
  • 一个可以综合的Verilog 写的FIFO存储器 内附文档说明
    一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
    2022-03-13 18:19:46下载
    积分:1
  • 696524资源总数
  • 103938会员总数
  • 55今日下载