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MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分：1
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ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分：1
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8psk
在matlab中8psk的调制和解调仿真程序(the modulation and demodulation of 8psk)
- 2013-05-02 09:54:07下载
- 积分：1
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min_max_finder_part1
最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)
- 2010-09-25 01:19:09下载
- 积分：1
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SIREN
An Alarm Project Writen in VHDL for FPGA Devices
- 2010-10-01 16:37:48下载
- 积分：1
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ptos
八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)
- 2018-05-02 19:43:25下载
- 积分：1
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webserver_c3
The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)
- 2014-03-23 20:00:14下载
- 积分：1
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signaltap_user_guide
signaltap 中文说明，内容详细。
ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)
- 2011-12-03 23:50:21下载
- 积分：1
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add
流水线乘法器与加法器
开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分：1
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application vhdl language adder design, compared with the design, With vhdl lang...
应用vhdl语言进行加法器的设计，比较器的设计，随着vhdl语言的应用越来越广泛，其重要性也更加明确。希望对大家有所帮助。-application vhdl language adder design, compared with the design, With vhdl language widely used, the importance of which was more explicit. We want to help.
- 2022-04-16 15:59:21下载
- 积分：1
