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sig_detect
使用信号功率计算，检测信号是否到达。从而控制后续模块，以减小系统功耗。(Signal power calculation, the detection signal to reach. To control follow-up modules to reduce system power consumption.)
- 2012-08-08 15:30:13下载
- 积分：1
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DDS-Basic-principle
DDS基本原理，详细讲述了DDS基本原理及设计技巧(DDS Basic principle)
- 2015-09-14 21:38:26下载
- 积分：1
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分别用分频比交错法及累加器分频法完成非整数分频器设计。...
分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
- 2022-01-25 23:28:15下载
- 积分：1
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agc
无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)
- 2020-10-22 14:27:23下载
- 积分：1
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Verilog written procedures for counting frequency meter module,
verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
- 2022-03-20 18:03:19下载
- 积分：1
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Divider can be very good VHDL divider realize the function of great help for beg...
除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助.
-Divider can be very good VHDL divider realize the function of great help for beginners.
- 2022-04-21 12:12:32下载
- 积分：1
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32bit_add_exercise
32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助(32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help)
- 2016-07-19 14:31:17下载
- 积分：1
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2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES...
2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH" s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
- 2022-07-17 15:40:45下载
- 积分：1
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FPGA realize for a good vga display routines, vhdl language.
针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
- 2022-01-24 09:45:51下载
- 积分：1
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clock_FPGA_verilog
简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))
- 2012-11-03 10:35:49下载
- 积分：1
