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spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换...
spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
- 2022-02-13 16:18:27下载
- 积分：1
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CGRA加密算法可重构
工作机制如下：
1、 系统上电,配置信息由片外加载到片上配置存储器中;
2、 执行某算法前，将此算法所有的配置包写入到配置包存储器中（配置包存储器包含在配置解析单元中）;
3、 配置解析单元解析配置索引,从配置存储器中选择相应的配置对可重构阵列及功能模块进行配置；
4、 阵列从外部中读取数据进行计算，计算结果写出到密文寄存器中；
5、 可重构阵列与功能模块计算的中间结果数据只与通用寄存器堆进行交互；
6、 阵列计算的中间结果通过通用寄存器堆缓存；
- 2023-05-25 10:10:04下载
- 积分：1
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FFT2
适用于NIOS II的1024点FFT C算法( 1024-point FFT C algorithm for NIOS II)
- 2010-12-04 15:32:44下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
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matlab_dspbuildings
matlab dsp building 工程欢迎下载(matlab dsp building )
- 2009-12-30 09:17:38下载
- 积分：1
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带FIFO的ov7670 FPGA应用程序，经测试可用
这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
- 2021-04-08 21:19:00下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入_2
说明： 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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elc_clock
verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)
- 2008-12-10 16:06:48下载
- 积分：1
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uart
通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分：1
