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多功能卡的源代码，verilog编写，用于多功能的数据接收
多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card
- 2022-09-30 12:00:08下载
- 积分：1
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用于fpga学习，共同分享学习经验和交流学习心得
用于fpga学习，共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning
- 2022-02-25 22:21:38下载
- 积分：1
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signalintegrity
信号完整的一些总结，非常实用，适合开始着使用(A book for signal integrated)
- 2014-08-08 16:45:47下载
- 积分：1
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tdma_code
tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)
- 2013-09-03 21:52:51下载
- 积分：1
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picorv32-master
说明： PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.
- 2020-06-24 21:40:01下载
- 积分：1
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万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！...
万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
- 2022-01-26 04:43:16下载
- 积分：1
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shuzizhong3
数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)
- 2016-05-27 11:41:22下载
- 积分：1
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这是用verilog硬件描述语言编的5分频代码
这是用verilog硬件描述语言编的5分频代码-This is verilog hardware description language code is compiled by five divider
- 2023-05-11 18:05:04下载
- 积分：1
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RS
说明： 本文设计了基于FPGA的，用verilog HDL语言描述的在伽罗华域GF（ ）上的RS（6,4）编码器。在ISE软件上用verilog HDL语言分别对每个模块进行描述，然后在软件上进行编译、仿真，最终实现RS（6,4）编码，下载之后用chipscope采集数据，分析符合仿真结果，达到设计的要求。(This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in software, the ultimate realization of the RS (6,4) encoding, after downloading by chipscope data acquisition, the analysis with the simulation results meet the design requirements.)
- 2017-08-25 17:59:14下载
- 积分：1
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facman
一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)
- 2021-03-31 07:39:09下载
- 积分：1
