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ethernet_tri_mode_rtl.tar
以太网控制器verilog，含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分：1
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bmistree_Project_Proposal
project proposal of verilog language that is gud for beginners
- 2011-04-25 00:31:03下载
- 积分：1
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用VHDL编写的计算器，能实现简单的加减乘除四则运算
用VHDL编写的计算器，能实现简单的加减乘除四则运算
- 2022-03-18 17:26:25下载
- 积分：1
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HM74YM
在QUARTUS II上实现（7,4）汉明码的译码VHDL语言设计((7,4)Hamming decoder)
- 2015-05-09 11:14:17下载
- 积分：1
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DIGITAL-PID
Use verilog language design DIGITAL-PID source
- 2016-12-26 09:41:15下载
- 积分：1
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一个完整的
一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！-A full-adder algorithm is based on the VHDL software emulation. Please download the reference!
- 2022-04-16 00:29:23下载
- 积分：1
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verilog
一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)
- 2016-12-12 10:02:20下载
- 积分：1
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ug_dsp_builder
本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)
- 2008-12-14 01:33:58下载
- 积分：1
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sync(shipintongbuxinhao)
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。(QuartusII-based environment to create the form of modular composite video sync signal.)
- 2009-04-06 12:49:46下载
- 积分：1
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一个同步有限状态机（FSM）的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分：1
