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高级加密标准AES的FPGA实现，支持128，256密钥长度格式
高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
- 2022-03-25 02:47:08下载
- 积分：1
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~ VHDL源代码的FFT IP核
FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
- 2022-02-25 23:54:48下载
- 积分：1
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primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used stora...
本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
- 2022-07-07 05:54:22下载
- 积分：1
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src
说明： 假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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zong
说明： quartusII 9.1，位同步提取电路，可以实现位同步时钟提取，其中包括分频器，和由D触发器以及与门组成的鉴相器模块。(Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate.)
- 2020-01-11 13:40:31下载
- 积分：1
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8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计...
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
- 2022-06-19 17:20:21下载
- 积分：1
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程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了...
程序在报告中，要 用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the
- 2022-07-17 18:13:27下载
- 积分：1
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BT656_RGB
BT656转RGB的算法实现代码，使用VORILOG语言编写(BT656-->RGB, verilog)
- 2021-02-24 09:39:39下载
- 积分：1
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FPGA实现CAN总线控制器源码
说明： 参照can芯片 saj1000控制器结构，写的can控制器(According to the structure of can chip saj1000 controller, the CAN controller is written)
- 2021-01-19 21:38:41下载
- 积分：1
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自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波....
自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波.-Their own design this year
- 2022-03-07 14:56:41下载
- 积分：1
