网站首页

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块...

于 2022-02-15 发布文件大小:237.96 kB

 0  94

下载积分: 2 下载次数: 1

我要下载

代码说明：

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块-the source for several sine ROM, has been compiled and passed, can be directly downloaded, not internal ROM containing sine table, the Acer ROM module

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

4-to-1
4选1数据选择器，有使能端控制，4个数据输入，2个地址端，1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)

2012-10-15 18:48:38下载

积分：1
LMS
verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确……(verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......)

2021-03-12 15:29:25下载

积分：1
n_bit_counter
n bit generic shift registers

2011-03-18 17:55:19下载

积分：1
fifo
异步FIFO的实现，很经典的三段式状态机的写法。(The realization of the asynchronous FIFO, very classic three-step writing state machine.)

2015-12-20 16:19:07下载

积分：1
verilog
基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)

2011-12-01 20:19:48下载

积分：1
SeggerEval_LPC2478
emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)

2012-08-04 13:54:29下载

积分：1
FPGA VERILOG 用DCFIFO实现跨时钟域的数据传输，已验证，直接可用...
FPGA VERILOG 用DCFIFO实现跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

2022-04-17 14:15:55下载

积分：1
Copy-of-DIGITAL-VLSI-DESIGN
a manual for design implementation of fpga and ASIC using verilog

2012-09-04 17:34:58下载

积分：1
AVS motion compensation circuit of VLSI Design and Implementation of a standard...
AVS运动补偿电路的VLSI设计与实现提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.

2022-01-21 20:19:47下载

积分：1
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source

2022-02-19 22:00:27下载

积分：1

696518资源总数
105547会员总数
4今日下载

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块...

0 个回复

热门标签

热门下载