-
Rabaey---Digital-Integrated-Circuits-2e-(Prentice
imp book for cmos technology
- 2015-04-10 15:39:16下载
- 积分:1
-
I2C interface standard modeling source
I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source
- 2022-01-24 12:53:13下载
- 积分:1
-
20190718
uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分:1
-
vhdl testbench的编写,textio的编写是一个难点,也是一个重点,而这是本人搜集的多篇关于textio的文章,同时附有简单注释!...
vhdl testbench的编写,textio的编写是一个难点,也是一个重点,而这是本人搜集的多篇关于textio的文章,同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!
- 2022-10-01 22:10:03下载
- 积分:1
-
文本液晶屏上显示计数器
这是一个项目,设计一个计数器和 vhdl 语言文本液晶屏上显示。为了文本液晶屏上显示我们都用 vhdl 语言设计了液晶显示控制器。
- 2022-03-15 04:31:20下载
- 积分:1
-
SPI_Master
此代码是SPI接口的Master的Verilog源代码,经上板测试是没有问题的,请大家放心使用
(This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)
- 2021-02-25 09:19:38下载
- 积分:1
-
Its-GPS-ranging-codes
GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)
- 2014-03-20 08:51:27下载
- 积分:1
-
uart16550 ip core UART VHDL source code
uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
- 2022-07-11 01:23:07下载
- 积分:1
-
rs_encoder
RS编码器的fpga实现,有TESTBench(RS encoder to achieve the fpga, and TESTBench)
- 2009-06-24 11:37:04下载
- 积分:1
-
FPGA实现12路pwm
采用vhdl语言实现12路的pwm波控制。-Language implementation using vhdl wave pwm control of the road 12.
- 2022-04-28 14:34:54下载
- 积分:1