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CPU
运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括:取指模块,译码模块,执行模块,访存模块,写回模块,寄存器组模块,控制相关检测模块,Forwarding模块。该CPU在TEC-CA实验平台上运行,并且通过Debugcontroller软件进行单步调试,实验表明,该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
- 2020-09-21 10:37:53下载
- 积分:1
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dianziqin
运用quartus 软件模拟的电子琴,实现按键出现不同音调的音乐。(Quartus software simulation using keyboard, keys appear to achieve different tones of music.)
- 2013-07-03 14:57:05下载
- 积分:1
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reed_solom
REEDSOLOMON source code
- 2010-04-30 17:44:52下载
- 积分:1
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scia_loopback_interrupts
TI F28027 SCI 源码,中断,FIFO,LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)
- 2020-11-18 15:29:40下载
- 积分:1
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xspUSB
关于usb调试相关测试 代码,用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)
- 2020-06-22 23:00:01下载
- 积分:1
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tlk2711test
用verilog语言实现了tlk2711serdes芯片的高速串行功能,包含工程与仿真文件,亲测可用(Using Verilog language to achieve a high-speed serial tlk2711serdes chip function, including the project and the simulation file, pro test available)
- 2020-12-29 23:39:00下载
- 积分:1
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该项目是用于执行4位arethmatic操作和逻辑操作…
The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E
- 2022-03-21 15:49:24下载
- 积分:1
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using VHDL keyboard scanning procedure can be slightly modified to use
使用VHDL键盘扫描程序,可以稍微修改一下使用
- 2022-03-05 17:56:26下载
- 积分:1
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一种基于LUT的预失真方法。其中的一部分,有参考价值。
一种基于LUT的预失真方法。其中的一部分,有参考价值。-one method of DPD based on LUT
- 2022-06-30 17:35:36下载
- 积分:1
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火车售票系统显示牌 FPGA VHDL
实现一个售票系统显示牌的设计,使用8位拨码开关输入车次,按键A按下一次表示该车次售出一张票,同时数码管显示该车次(K+3个数码管显示拨码开关对应的十进制数,如拨码开关值为”00010101”时,则车次为 “K021”)及该车次剩余的票数(每车次总票数值为100),若K021次车还剩余78张票,则数码管显示“K021-78”。要求至少存储3趟车次信息,例如车次K020,K021,K022 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2023-06-18 07:30:03下载
- 积分:1