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它的译码器的VHDL程序
it s vhdl program for decoder
- 2022-11-23 15:15:04下载
- 积分:1
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高速双端口RAM的vhdl实现。包含仿真波形
高速双端口RAM的vhdl实现。包含仿真波形-High-speed dual-port RAM realize the VHDL. Contains the simulation waveform
- 2023-08-22 14:25:04下载
- 积分:1
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3he11
产生SH,SP,RS,SP,φ1,φ2驱动脉冲,用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)
- 2013-05-15 20:50:30下载
- 积分:1
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M_M
此为数学形态滤波器消燥的代码,用于一维信号,涉及一个具体的例子,需要的话可以自己修改,修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)
- 2013-08-29 21:36:37下载
- 积分:1
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alu3
用verilog语言编写,一个8-bit ALU,可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分:1
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tPad_Camera
tPad DE2-115/70开发板可用的摄像头采集、显示程序,QT10.0以上环境可用,原装代码,可以进行修改加以使用,如使用到倒车影像系统中,视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)
- 2020-07-09 19:58:55下载
- 积分:1
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dct
基于FPGA的图像压缩算法程序,自己写的,可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)
- 2011-10-23 00:54:17下载
- 积分:1
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THU微纳电子系ic设计课程大作业CNN
说明: THU微纳电子系ic设计课程大作业,使用verilog实现CNN加速器,含一层卷积和池化,仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)
- 2020-07-06 20:18:57下载
- 积分:1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分:1
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AD9648_ver
FPGA通过SPI总线配置AD采集芯片AD9648的程序,Verilog实现 (FPGA configuration via SPI bus chip AD9648 AD acquisition procedures, Verilog realization)
- 2013-09-27 17:28:14下载
- 积分:1