登录
首页 » VHDL » URAT 部分VHDL源码 大家多多支持 哈哈

URAT 部分VHDL源码 大家多多支持 哈哈

于 2022-02-20 发布 文件大小:16.99 kB
0 145
下载积分: 2 下载次数: 1

代码说明:

URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • fft
    说明:  用VERILOG语言实现的频谱分析仪(FFT)(VERILOG language with the Spectrum Analyzer (FFT))
    2009-08-09 16:30:23下载
    积分:1
  • TOPWAY-UC1698-AppNote-V0.2
    UC1698U驱动160*160LCD中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)
    2013-05-23 09:25:56下载
    积分:1
  • hgb_pci_host
    说明:  内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持: 1、 对目标PCI_T进行配置; 2、 对目标进行单周期读写; 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的(There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of)
    2008-09-16 18:57:25下载
    积分:1
  • AMBA
    AMBA总线规范,能对从事嵌入式的同行们有一些帮助,让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)
    2012-12-06 20:35:22下载
    积分:1
  • fenpinqi de vhdlchengxu gongnengfnagzhen,政
    分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
    2022-02-21 21:03:34下载
    积分:1
  • adconfig
    AD9268的配置Verilog实现,程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)
    2021-04-15 16:58:54下载
    积分:1
  • chengxu
    设计制作一个可容纳4组参赛者的数字智力抢答器,每组设置一个抢答按键; 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后,若参加者按抢答键,则该组指示灯亮并用组别显示抢答者的组别。此时,电路具有自锁功能,使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分,抢答后主持人计分,答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
    2012-06-10 12:58:44下载
    积分:1
  • FPGA2-DSP2-EDMA
    例程是基于quartus的,FPGA通过EMIF给DSP发送数据,里面包含了一个简单的状态机和一个基于IP核的fifo,适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
    2020-12-04 16:09:24下载
    积分:1
  • LCD的Spartan3E FPGA VI
    LCD SpartaN3E fpga vi
    2022-01-29 03:37:34下载
    积分:1
  • 简单的APB I2S接口
    简单的apb i2s接口,verilog代码,包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)
    2019-01-18 16:52:05下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载