-
rscode
R S编 解 码 实 现 代 码
verilog语言(RS CODE AND ENCODE)
- 2013-05-19 16:19:55下载
- 积分：1
-
fft64
verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分：1
-
xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分：1
-
DAC_VHDL
DAC VHDL code using SPI method
- 2016-11-09 19:53:01下载
- 积分：1
-
Verilog-HDL-tutorial
verilog HDL经典的入门书籍，内容很详细，讲了许多实例，适合硬件描述语言初学者。(verilog HDL classic introductory book, the content is very detailed, spoke many instances, suitable hardware description language for beginners.)
- 2013-10-08 20:21:51下载
- 积分：1
-
学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法....
学习使用HDL Bencher生成测试积累，并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
- 2022-02-28 22:36:00下载
- 积分：1
-
Desktop4
combinational circuits code in vhdl
- 2018-08-13 17:33:14下载
- 积分：1
-
08_4_hdmi_loop
HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)
- 2020-06-17 09:00:02下载
- 积分：1
-
是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间...
是用于pci开发的核，可以将硬件的信息映射到然间上来 节省出开发人员用于了解硬件的时间 -Pci developed for nuclear, hardware information can be mapped to the inter-ran up to save the developers time to understand the hardware
- 2022-01-26 02:12:56下载
- 积分：1
-
this is the for a equiripple filter
this the for a equiripple filter-this is the for a equiripple filter
- 2022-04-17 20:07:48下载
- 积分：1
