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Fast_median_filter
FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
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电梯控制器
这个项目的目的是要为想要建立时序控制电路的数字化设计实验提供一个模型。设计的电路模拟电梯的运作。仿真器有输入来控制电机，其方向、 门、 灯等。它还具有输出信号调用按钮、 液位传感器和安全。使用 Verilog 硬件描述语言和使用四个 22V10 小的可编程逻辑器件 （学童） 实现，设计的电路。提供了三级安装示例电梯控制器。
- 2023-06-13 14:05:03下载
- 积分：1
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matlab
真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)
- 2021-03-16 22:39:21下载
- 积分：1
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multiplexersemultiplexer
this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2009-12-21 18:11:27下载
- 积分：1
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C4gx15_starter_qsys_pcie_gen1x1
PCIe demo sample code
- 2020-12-09 16:39:19下载
- 积分：1
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UART_TEST
通过设置串口的波特率、起始位、检验位等参数，进行FPGA的串口通讯(By setting the baud rate, the starting bit, the test bit and other parameters of the serial port, the serial communication of FPGA is carried out)
- 2017-07-08 11:54:13下载
- 积分：1
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plldesign
pll(phase locked loop) is used to fix the circuit to particular frequency
- 2014-03-18 17:14:26下载
- 积分：1
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状态机的显示
此代码是一个状态机（西班牙）对FPGA nexys3 7段显示器显示一个4个字母。该代码是verilog语言进行
- 2023-04-11 18:10:03下载
- 积分：1
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32位-33M 从模式(target)PCI接口参考设计_lattice
说明： 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考(32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only)
- 2005-10-24 19:35:04下载
- 积分：1
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dianyuan
实现按键控制AD三通道的电源转换的功能。(AD three buttons control channel to achieve power conversion)
- 2015-04-23 16:20:49下载
- 积分：1
