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Quartus
QuartusII多路选择器,数字电路环境，大三EDA技术实验(Quartus,chosen conductos in matheathics field)
- 2012-10-30 16:26:11下载
- 积分：1
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ahb_sramc_svtb
ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)
- 2021-05-14 14:30:02下载
- 积分：1
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08_4_hdmi_loop
HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)
- 2020-06-17 09:00:02下载
- 积分：1
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verilog fifo 代码
FIFO is a First-In-First-Out memory queue with control logic that manages
the read and write operations, generates status flags, and provides optional
handshake signals for interfacing with the user logic. It is often used to
control the flow of data between source and destination. FIFO can be
classified as synchronous or asynchronous depending on whether same clock
or different (asynchronous) clocks control the read and write operations. In
this project the objective is to design, verify and synthesize a synchronous
FIFO using binary coded read and write pointers to address the memory
array. FFIO full and empty flags are generated and passed on to source and
destination logics, respectively, to pre-empt any overflow or underflow of
data. In this way data integrity between source and destination is maintained.
The RTL description for the FIFO is
- 2022-05-22 08:44:13下载
- 积分：1
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booth4
4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写(4-bit adder booth algorithm, the learning of computer organization help, verilog language)
- 2010-09-27 04:49:51下载
- 积分：1
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CPU-Verilog
说明： 简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
- 2020-06-23 19:40:01下载
- 积分：1
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clk_div3
在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分：1
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CIC
Efficient CIC filter Implementation using VHDL
- 2010-11-19 08:54:23下载
- 积分：1
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SD卡读取图片显示例程
基于verilog的SD卡读取图片显示例程的实验
基于verilog的SD卡读取图片显示例程的实验
基于verilog的SD卡读取图片显示例程的实验
基于verilog的SD卡读取图片显示例程的实验
基于verilog的SD卡读取图片显示例程的实验
- 2022-03-21 20:22:44下载
- 积分：1
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AskPsk
说明： ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)
- 2005-11-26 09:14:32下载
- 积分：1
