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fifo_ref_timing
first in first out 的说明文档以及时序图
对学习FIFO很有帮助(first in first out the documentation and the timing diagram helpful in learning FIFO)
- 2010-07-21 21:43:36下载
- 积分：1
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This is a simple routine FPGA is mainly based on FPGA
这是一个FPGA的简单例程，主要是基于FPGA的232串口通信的例程-This is a simple routine FPGA is mainly based on FPGA-232 serial communication routines
- 2022-03-06 20:54:43下载
- 积分：1
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fifo
FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分：1
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V2.tar
SDIO slave, written in verilog, does not support SPI mode.
- 2021-04-05 16:59:04下载
- 积分：1
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led 点阵显示led――rom实现，功能模块分离 就爱可根据卡加大公开吉安市贷款给经济...
led 点阵显示led――rom实现，功能模块分离 就爱可根据卡加大公开吉安市贷款给经济 -led dot matrix display led-- rom realized, functional modules can be separated on the basis love Cagayan open to the public Ji"an City loans to the economy
- 2022-04-18 05:01:17下载
- 积分：1
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Verilog1
这个程序为通信中的16QAM调制程序，可用于无线或有线通信系统的调制仿真之用。(The 16QAM modulation communication this program can be used for wireless or wired communication system modulation simulation purposes.)
- 2013-05-16 17:30:08下载
- 积分：1
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使用Ｖeriolog hdl 编写手机屏测试程序．
使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.
- 2023-04-25 00:20:03下载
- 积分：1
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This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
- 2022-03-23 13:41:19下载
- 积分：1
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ces_svtb_2011.12
synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。(synopsis sv training lab)
- 2021-04-19 11:18:51下载
- 积分：1
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led
基于fpga的led点阵控制系统软件程序设计(Led dot matrix control system based on fpga software program design)
- 2013-01-14 11:50:35下载
- 积分：1
