-
用VHDL的玛摩尼的ASIC设计
ASIC Design using VHDL by Shyam Mani
- 2022-02-21 17:12:20下载
- 积分:1
-
使用Veriolog hdl 编写手机屏测试程序.
使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.
- 2023-04-25 00:20:03下载
- 积分:1
-
this a spartan 3E base project file.
this is the project of game in which vga...
this a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.-this is a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.
- 2023-07-29 01:40:03下载
- 积分:1
-
watch
数字钟,简单的数电应用,电子表源程序,常用也使用-watch
- 2022-04-18 14:17:50下载
- 积分:1
-
BLAST_QR1
MIMO系统采用QR检测算法的MATLAT仿真程序(mimo qr)
- 2009-07-15 08:09:01下载
- 积分:1
-
Spartan6_GTP_PCIe_xfest_2009_v1_0
采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)
- 2012-08-30 10:01:33下载
- 积分:1
-
基于VHDL的rsc(7,5)递归卷积编码器
rsc递归卷积编码器是turbo码的分量编码器,递归相对于普通的卷积码多了一个反馈,拥有更好地重量谱分布和更加的误码率特性,且码率越高,信噪比越低其优势越明显。利用D触发器组成的rsc生成器,逻辑思维简单,里面包含有测试波形以及测试的结果
- 2022-06-28 16:38:10下载
- 积分:1
-
alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分:1
-
fir_lms
基于FPGA的自适应滤波器的实现。采用Verilog编程,2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)
- 2009-04-27 12:06:25下载
- 积分:1
-
VGA控制器的VHDL,得出3条线
vga controller vhdl, it draws 3 lines -vga controller vhdl, it draws 3 lines
- 2022-01-25 16:45:25下载
- 积分:1