-
Some_classic_examples_of_VHDL_language_source_code
VHDL语言的一些经典实例源代码,包括状态机,时序电路,组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)
- 2010-07-11 12:50:06下载
- 积分:1
-
cic_compiler_ds613
说明: 国外的CIC补偿滤波器设计文件,非常有用(Abroad, CIC compensation filter design files, very useful)
- 2010-03-21 13:56:49下载
- 积分:1
-
AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
-
ran_num_generator.tar
vhdl random numbergenerater
- 2013-04-10 16:31:28下载
- 积分:1
-
verilog spi file with testbench
verilog spi file with testbench
- 2022-06-11 23:50:30下载
- 积分:1
-
gtx_aurora_zc706_example
Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议,通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式,以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
- 2018-01-23 08:53:37下载
- 积分:1
-
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过...
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛,本例用VHDL描述了一个锁相环作为参考,源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上;顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
- 2022-02-01 22:27:36下载
- 积分:1
-
signaltap_user_guide
signaltap 中文说明,内容详细。
ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)
- 2011-12-03 23:50:21下载
- 积分:1
-
My_PMSM_SOPC
基于FPGA的PWM波生成程序,用于控制步进电机。(A PWM wave generater for driving stepper motor.)
- 2018-05-07 20:05:05下载
- 积分:1
-
T13_USB
本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输,实现了pc端接收来自FPGA开发板的数据,并显示条纹,具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)
- 2011-01-05 15:10:38下载
- 积分:1