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FPGA正弦信号发生器
基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)
- 2020-11-10 10:59:46下载
- 积分：1
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jianpan
说明： 一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分：1
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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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(Avalon-ST)-interface_from_liu
IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)
- 2012-09-16 13:41:57下载
- 积分：1
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cordic
基于VHDL语言编写，可下载到FPGA板子上实现的cordic算法实现的设计，并用该算法实现sin和cos的计算，计算结果显示在数码显示管上，已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)
- 2013-03-21 16:52:41下载
- 积分：1
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MT9M001
FPGA驱动MT9M001的verilog代码，里面还有ddr3部分将图像数据进行存储，lcd进行图像显示，里面的摄像头驱动部分很详细，大家可以多研习研习(Verilog driver MT9M001 code, which is also the DDR3 image data storage, LCD display, which drives the part is very detailed, we can learn more)
- 2020-07-10 13:48:54下载
- 积分：1
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一个小程序,弹跳消除电路,可消除按健的毛刺干扰
一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference
- 2022-05-14 03:36:36下载
- 积分：1
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seg7
SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分：1
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ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me....
ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
- 2022-02-02 17:09:38下载
- 积分：1
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系统设计
说明： 基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分：1
