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Sys-gen
System Generator
- 2020-10-25 16:40:00下载
- 积分：1
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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
- 2022-02-11 16:15:23下载
- 积分：1
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含移动储能单元的微网优化调度模型研究_吴婷
含移动储能的分布式电能优化调度，模型的处理与改进(Processing and improvement of distributed power optimization scheduling with mobile energy storage)
- 2018-10-17 10:18:53下载
- 积分：1
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Modulator70
个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)
- 2011-07-29 15:16:30下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分：1
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基于EPM1270
基于EPM1270的EProm at24c02 驱动-Based on the EPM1270
- 2022-02-27 00:52:37下载
- 积分：1
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dianziqin
运用quartus 软件模拟的电子琴，实现按键出现不同音调的音乐。(Quartus software simulation using keyboard, keys appear to achieve different tones of music.)
- 2013-07-03 14:57:05下载
- 积分：1
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sampleverilog
图像采集、存储控制verilog源代码(Image acquisition, storage, control of Verilog source code)
- 2021-04-15 22:28:54下载
- 积分：1
