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data_rom
正弦信号发生器,用VHDL来完成,抗干扰能力较强,(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)
- 2009-07-15 22:44:02下载
- 积分:1
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29_ad9226_test
说明: 用Verilog编写ad_9866的相应程序,在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)
- 2019-06-24 16:43:27下载
- 积分:1
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MP3译码器的VHDL代码
MP3解码器的VHDL源代码 ,很实用的,设计时可以参考 ,很罕见的完整MP3 decoder源码 -VHDL code for MP3 decoder
- 2022-05-07 23:05:49下载
- 积分:1
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CfgDDS_9910
dds ad9910配置的verilog hdl程序,模块化设计,输入待配置的数据,字长,启动信号,即可自动产生时序,完成一次配置,模块还有done握手信号,方便用户调用时,反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)
- 2015-04-21 22:03:50下载
- 积分:1
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数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位
数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl)
can be used to test frequency (8bit)
- 2022-04-10 23:14:01下载
- 积分:1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
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quartus-mult
mult,在quartusII中,以模块输入形式,仿真乘法器mult,得到时序图和功能图(a simulation example of mult)
- 2012-10-17 14:22:11下载
- 积分:1
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AM-modulated-learning-ladder
AM modulated learning ladder
- 2015-07-15 09:42:45下载
- 积分:1
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一个vhdl实现的hamming码编码器
一个vhdl实现的hamming码编码器-an hamming coder using vhdl
- 2023-02-25 17:20:03下载
- 积分:1
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adder16b
说明: 潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)
- 2009-07-23 17:02:22下载
- 积分:1