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CLZ32
针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分：1
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my_kmp_matching
说明： KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)
- 2011-03-14 09:28:01下载
- 积分：1
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EP2C70F896C6N-pins
将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
- 2020-12-09 11:09:21下载
- 积分：1
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nerualnetwork
本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。
(In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)
- 2008-12-14 01:37:03下载
- 积分：1
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04_uart_test
说明： 基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)
- 2021-03-14 13:43:49下载
- 积分：1
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AD9764
一个AD9764的基于FPGA的驱动，希望对有需要的朋友有所帮助(An AD9764 FPGA-based drive, we want to help a friend in need)
- 2013-09-05 01:48:57下载
- 积分：1
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一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了...
一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms
- 2022-08-14 17:54:21下载
- 积分：1
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fft_32k_readme_v1_0_0
Fast Fourier Transform (FFT) 32K Point Design contains
information about the design example
- 2018-10-11 15:11:54下载
- 积分：1
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0720_03_AD_uart
说明： 基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)
- 2019-01-21 20:52:46下载
- 积分：1
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add_verilog
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分：1
