登录
首页 » VHDL » vcp201_code是FPGA的源代码。

vcp201_code是FPGA的源代码。

于 2023-06-03 发布 文件大小:585.54 kB
0 19
下载积分: 2 下载次数: 1

代码说明:

VCP201_CODE is a FPGA source code.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • GMSK
    说明:  高斯最小频移键控(Gaussian Filtered Minimum Shift Keying),这是GSM系统采用的调制方式。数字调制解调技术是数字蜂窝移动通信系统空中接口的重要组成部分。GMSK调制是在MSK(最小频移键控)调制器之前插入高斯低通预调制滤波器这样一种调制方式。GMSK提高了数字移动通信的频谱利用率和通信质量。(Gauss Filtered Minimum Shift Keying is a modulation method used in GSM system. Digital modem technology is an important part of air interface of digital cellular mobile communication system. GMSK modulation is a method of inserting a Gaussian low-pass pre-modulation filter before the MSK (minimum frequency shift keying) modulator. GMSK improves the spectrum utilization and communication quality of digital mobile communication.)
    2019-06-14 09:18:30下载
    积分:1
  • Verilog HDL language proficiency of a good cpu code
    veriloghdl语言熟练的一个很好的cpu代码
    2022-10-31 00:00:03下载
    积分:1
  • 5L_SVPWM_ANPC_CPLD
    基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)
    2020-12-14 16:19:15下载
    积分:1
  • ahdl--sine-wave-code-with-rom-look-up-table_imp
    hi this is an verilog codes
    2011-11-11 14:30:21下载
    积分:1
  • Verilog_Ip_RAM
    说明:  altera ram ip教程。对RAM进行读写操作,写32个数据到RAM中,再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)
    2020-08-17 11:38:21下载
    积分:1
  • 输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2...
    输入正确密码显示绿灯亮 错误时红灯亮并发出警报 运行环境为matplaux 2-a afdg jhg dfgh r fbnrfer
    2023-02-24 12:15:03下载
    积分:1
  • CXFlt
    通信系统中的基带信号处理中的成型滤波器代码,已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)
    2015-03-24 09:43:05下载
    积分:1
  • dpwm_8bit
    数字脉冲宽度调制,将输入的数字信号转换为对应占空比的模拟波形(Digital pulse width modulation, the digital signal is converted to the corresponding input of the duty cycle of the analog waveform)
    2020-06-28 16:00:02下载
    积分:1
  • apb timer
    说明:  是基于apb总线下的timer外设的rtl代码,主要包括apb_timer的master逻辑verilog,以及相应的开发文档,包括寄存器的描述,功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
    2019-01-25 16:54:02下载
    积分:1
  • 自己写得一个关于sine(32X24)的程序
    自己写得一个关于sine(32X24)的程序-own written on a sine (32X24) procedures
    2022-02-28 22:21:58下载
    积分:1
  • 696524资源总数
  • 103938会员总数
  • 55今日下载