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within waveform generator, Adder, classic dual
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分：1
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VHDL与Verilog的比较
VHDL与Verilog的比较-VHDL and Verilog comparison
- 2022-04-14 10:03:59下载
- 积分：1
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UART(RS232)
用VERILOG语言实现的通用异步串行收发器（RS232收发器），波特率可设置，通讯稳定，已成功应用于实际项目。(VERILOG language with universal asynchronous serial transceivers (RS232 transceiver), the baud rate can be set, communication stability, has been successfully applied in actual projects.)
- 2021-04-01 10:59:08下载
- 积分：1
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test bench for alu 6 functions
test bench for alu 6 functions
- 2022-03-02 06:50:51下载
- 积分：1
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myAdc9248
CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)
- 2017-01-31 21:55:26下载
- 积分：1
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LightControl
说明： 经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)
- 2011-03-05 09:49:32下载
- 积分：1
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CPLD
基于CPLD 的光电脉冲码盘
信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design
- 2022-08-10 19:02:11下载
- 积分：1
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kt1
基于FPGA的可控100进制可逆计数器，运行环境maxplus(Controlled 100 hex reversible counter FPGA-based operating environment maxplus)
- 2012-05-17 12:19:54下载
- 积分：1
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ldpc-for-fpga-decoding
ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)
- 2021-04-12 21:38:56下载
- 积分：1
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(Avalon-ST)-interface_from_liu
IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)
- 2012-09-16 13:41:57下载
- 积分：1
