-
3Code_for_Medx
3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。
(3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)
- 2012-07-30 00:49:45下载
- 积分：1
-
File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分：1
-
FPGA DDS
使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分：1
-
ldpc
低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)
- 2014-04-09 10:24:51下载
- 积分：1
-
NCO of the VHDL process is the use of nuclear
NCO的VHDL程序，是利用IP核生成的，超好的，快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
- 2022-03-22 15:41:09下载
- 积分：1
-
VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分：1
-
ldpc_decoder_802_3an
LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)
- 2018-07-23 15:01:20下载
- 积分：1
-
256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分：1
-
ethernet_mii_udp_1
说明： Verilog开发的，MII接口的百兆以太网UDP代码(100 megabit Ethernet UDP code of MII interface)
- 2020-03-20 16:19:21下载
- 积分：1
-
the booth algorithm to implement the 32bit 's multiplication.
the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.
- 2022-10-16 05:40:03下载
- 积分：1
