登录
首页 » VHDL » In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...

In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Ver...

于 2022-03-16 发布 文件大小:463.34 kB
0 120
下载积分: 2 下载次数: 1

代码说明:

在Altera芯片2C35F672平台上的FFT程序,采用DSPBuilder5.0,生成Verilog文件。开发环境:QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 111186763ddqpsk
    说明:  这是一个关于OQPSK的Matlab程序 这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)
    2010-04-21 12:41:59下载
    积分:1
  • 帧同步信号FPGA实现代码(可正常运行)
    通信系统帧同步信号的设计与实现,巴克码识别器系统完整VHDL程序,本人课程设计,完全能正常运行,程序运行环境为Quartus II 7.2 (32-Bit),win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流,共同学习!!
    2022-03-24 07:45:00下载
    积分:1
  • shuangerxuanyi
    说明:  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)
    2010-04-10 12:02:49下载
    积分:1
  • CircuitDesignwithVHDL[1]
    这主要是学习vhdl和fpga设计的一些资料(study for vhdl and fpga)
    2009-05-13 09:31:26下载
    积分:1
  • verilog 232串口收发程序 在开发板上测试成功过
    verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
    2022-02-11 11:33:57下载
    积分:1
  • 用VHDL编写的FIR数字滤波器的程序可以用在FPGA工作。
    FIR数字滤波器程序,采用vhdl编写,可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
    2022-08-15 20:37:14下载
    积分:1
  • Crazy_FPGA_Examples
    crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码,主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)
    2020-10-19 18:47:25下载
    积分:1
  • 13.2_MotionDetec
    基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)
    2020-10-23 20:57:22下载
    积分:1
  • adder2
    此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ,特别是模为 60 的 BCD码加法计数器,这是我目前发现的最优源代码,应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)
    2010-10-30 15:14:06下载
    积分:1
  • lab7_files
    关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)
    2013-02-01 11:02:38下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载