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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分：1
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yuandaima
以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分：1
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用VHDL编写的EPP通信协议，可以同时收发字节
用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
- 2022-05-22 02:38:48下载
- 积分：1
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algorithm_design_and_logic_implemention
本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
- 2009-11-11 21:19:03下载
- 积分：1
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ahb2apb-master
ahb to apb master and slave
- 2018-03-06 00:27:56下载
- 积分：1
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adder.ripple
an 16 bit ripple carry adder
- 2012-11-02 23:20:33下载
- 积分：1
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irig_b
用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)
- 2021-04-06 14:49:03下载
- 积分：1
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8051core-Verilog
8051core-Verilog FPGA
- 2021-02-02 21:59:59下载
- 积分：1
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这是一个代码为华勒斯树乘法器
This a code for wallace tree multiplier-This is a code for wallace tree multiplier
- 2022-02-03 07:00:25下载
- 积分：1
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DigitalClock
数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)
- 2013-05-26 09:25:23下载
- 积分：1
