-
frame_decode_and_encode
一个用Verilog编写的编帧、解帧及码速匹配的程序,相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)
- 2006-07-12 15:10:07下载
- 积分:1
-
有关verilog的硬件实现VGA设计的代码。
有关verilog的硬件实现VGA设计的代码。-On the Verilog hardware design realize VGA code.
- 2022-07-17 09:16:28下载
- 积分:1
-
HwLog10
用verilog写的,基于查表法实现的LOG10运算器,在Altera FPGA中应用。(It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.)
- 2021-04-07 15:59:01下载
- 积分:1
-
compa
comparator code for micarowind
- 2015-03-28 17:18:49下载
- 积分:1
-
telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
-
整个工程代码
掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序,熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)
- 2019-01-21 17:21:27下载
- 积分:1
-
hdlc
hdlc协议的封装与解析,fsc校验,完整的例程代码(Decode and Encode an HDLC packet ,using FCS16 calculation)
- 2015-09-21 11:20:55下载
- 积分:1
-
用VHDL实现视频控制程序(实现对图像的采集和压缩)
用VHDL实现视频控制程序(实现对图像的采集和压缩)-Using VHDL video control procedures (the achievement of the image acquisition and compression)
- 2022-12-07 16:40:03下载
- 积分:1
-
S6_VGA
1。源文件保存在src目录,QII的工程文件保存在Proj目录;
2。程序实现的功能是在VGA显示器上显示彩色条纹,共8种颜色,
可以使用嵌入式逻辑分析仪观测信号;
3。modelsim仿真文件在proj--simulation--modelsim中(1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim)
- 2012-11-04 18:26:48下载
- 积分:1
-
BT1120转GTX详细设计方案
bt1120设计方案,描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)
- 2020-06-25 05:40:02下载
- 积分:1