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ALTERA嵌入式设计大赛获奖作品文章,非常适合DE2开发参考
ALTERA嵌入式设计大赛获奖作品文章,非常适合DE2开发参考-ALTERA Embedded Design Competition Prize-winning article, very suitable for the development of reference DE2
- 2022-04-07 11:00:16下载
- 积分:1
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FPGA中按键弹跳消除模块的研究与应用,原理和例子都非常好
FPGA中按键弹跳消除模块的研究与应用,原理和例子都非常好-FPGA to eliminate bounce in key research and application modules, principles and examples are very good
- 2022-02-20 02:12:06下载
- 积分:1
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FPGA锁相环实验
说明: FPGA锁相环实验:
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
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400rdm
用于FPGA的学习,大家值得借鉴,可以好好学习一下(this is for fpga and you can use this.)
- 2020-06-16 15:20:02下载
- 积分:1
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logique
ainsi permettre la simplification du calcul ultérieur des courants et tensions dans une partie de celui-ci.
La méthode de Norton abouti invariablement au circuit suivant soit une
source de courant, une résistance parallèle (correspond à la Ri de la
source) et une résistance de charge. La résistance de charge est une des
- 2014-11-14 09:07:44下载
- 积分:1
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实用的程序代码,希望对大家有用,已经调试通过
实用的程序代码,希望对大家有用,已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through
- 2022-10-20 00:55:03下载
- 积分:1
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vhdl adder with two input 4
vhdl adder with two input 4-bit and output of 4 bits and carry
- 2022-11-16 00:35:03下载
- 积分:1
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The number of organ controller Verilog code, with English Notes.
数字电子琴控制器的VERILOG代码,含中文注释.-The number of organ controller Verilog code, with English Notes.
- 2022-02-28 22:36:52下载
- 积分:1
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CODE_VHDL_COUNTING 0 到 9,使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
CODE_VHDL_COUNTING 0 到 9,使用按钮 (Đếm 慈 0 đến 9 hiển 施耐 1 带领 7 đoạn sử dụng nút nhấn để điều khiển)
Với bài này tôi sử dụng một nút nhất để một nút nhấn đế bắt đầu đếm dữ liệu 将重置。
- 2022-07-25 16:14:59下载
- 积分:1
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Xilinx
Xilinx的I2C总线控制器,verilog版本,文档号是XAPP333,可到Xilinx网上查找具体说明,有对应的VHDL版本的-Xilinx
- 2022-07-04 07:06:06下载
- 积分:1