-
coreahblite代码
amba ahblite总线时序转并口时序，可访问sram/flash/mram，适用于smartfusion2系统，arm内核对外进行数据访问。
- 2023-08-27 04:00:03下载
- 积分：1
-
单周期cpu
说明： 该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)
- 2019-12-14 20:55:42下载
- 积分：1
-
nios_ruanhe_spi_3
这是我自己写的一个摄像头数据存储SD卡程序，quartus的verilog编写，摄像头采用自己添加的外设接口，数据采用dma采集，SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测，有兴趣的可以测测，初学者可以参考学习，写的代码有点乱，如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)
- 2015-09-18 11:39:07下载
- 积分：1
-
2位并行加法器初学者必看初步了解FPGA
2位并行加法器初学者必看初步了解FPGA-two count
- 2023-07-28 14:05:03下载
- 积分：1
-
ZBT-sram控制器VHDL.doc
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com) - URJC
FRAV Group (www.frav.es)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at)
visengi (dot) com)
--
-- Create Date: 12:39:50 06-Oct-2008
-- Pr
- 2022-03-02 23:54:43下载
- 积分：1
-
通过VGA接口获取视频输出的VHDL代码
vhdl code for obtaining video output through vga port
- 2022-02-04 13:35:30下载
- 积分：1
-
这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途....
这是一本关于VHDL编程的书籍,网上突然发现的,相信对相关人员会有所用途.-This is a book on VHDL programming, on-line suddenly found, I believe that the relevant staff will be use.
- 2023-02-06 08:50:07下载
- 积分：1
-
cordic
cordic算法，实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)
- 2020-06-29 14:00:01下载
- 积分：1
-
基于FPGA的八位RISC CPU的设计
基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
- 2022-04-07 11:51:38下载
- 积分：1
-
对于多个子分频的Verilog代码
verilog分频器代码
分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
- 2022-10-15 03:40:06下载
- 积分：1
