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时序逻辑与组合逻辑（VHDL）
代码使用应用于 FPGA的VHDL代码，主要是告诉大家时序逻辑和组合逻辑的应用场合和区别，希望能够对大家有所帮助
- 2022-10-19 04:15:03下载
- 积分：1
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4. If a modified source code is distributed, the original unmodified
4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.
- 2022-01-21 00:25:44下载
- 积分：1
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FPGA的SRAM存储器的控制程序，包括时序测试
FPGA的SRAM存储器的控制程序，包括时序测试-FPGA
- 2023-03-19 08:20:03下载
- 积分：1
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project_zy
超声波测距程序 适用传感器HC-SR04(The application of sensor HC-SR04 for ultrasonic range finder)
- 2017-12-25 18:05:12下载
- 积分：1
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FDPIM_Encode
关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分：1
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此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具
此ip核是xvga视频接口控制器，主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx
- 2022-01-25 16:44:58下载
- 积分：1
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基于无源蜂鸣器和矩阵按键的电子琴系统设计
基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分：1
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VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
- 2022-01-20 23:11:51下载
- 积分：1
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Simple ADC of signal and LED indication
这是一个VHDL项目，用于在VIRTEX-4 xc4vsx35 FPGA板中执行接收信号的14位ADC。
- 2022-01-24 15:38:32下载
- 积分：1
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verilog-lfsr-master
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分：1
