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FPGA_UART
说明： FPGA串口实现。
发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)
- 2010-05-04 00:15:23下载
- 积分：1
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zhuangtai
状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)
- 2007-11-11 21:36:15下载
- 积分：1
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Continuous_acoustic_emission_board
多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分：1
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rs232
用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)
- 2015-08-21 20:26:16下载
- 积分：1
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Риторика_Зачетная работа
access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分：1
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sd_vga_photo
fpga读取sd卡内容并且通过vga接口在显示器上显示图片(fpga read sd card contents and by vga interface to display pictures on the monitor)
- 2016-04-18 13:53:44下载
- 积分：1
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led_water
酷睿系列流水灯通用程序，来回往返流水，点亮led(ledwater for ep2c8q208c8)
- 2017-11-11 00:57:15下载
- 积分：1
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scramble
VHDL编写加扰和解扰程序，程序连在一起仿真正确，并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem
- 2022-03-03 18:10:46下载
- 积分：1
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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分：1
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atom.2007.12.tar
Cores are generated from Confluence a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C
- 2008-05-12 10:13:23下载
- 积分：1
