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eetop.cn_cordic_sqrt
cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)
- 2018-06-29 08:47:12下载
- 积分：1
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multifre
说明： 资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料，包括鉴相信号如何倍频，机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)
- 2010-04-26 15:56:20下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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FPGA
数字钟的VHDL语言程序，包含了好几个模块，是毕业设计的优秀程序，值得下载！(VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!)
- 2015-08-31 21:07:44下载
- 积分：1
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pidd
verilog实现增量式PID算法，实测可用，带modelsim仿真(PID algorithm by verilog)
- 2017-10-20 19:26:34下载
- 积分：1
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lab1(mka)
RGB vga driver for manipulating the colours of a given image buffer. The code has beeen written in vhdl
- 2011-04-15 18:11:48下载
- 积分：1
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FPGA DDS
使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分：1
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cf_ad9649_ebz_edk_14_4_2013_03_19.tar
说明： ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)
- 2020-06-28 14:00:02下载
- 积分：1
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ddsProm
dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)
- 2013-06-13 10:07:16下载
- 积分：1
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Shift_reg
一个简单移位寄存器代码，verilog HDL编写(a simple shift register example，write with verilog HDL)
- 2012-03-26 21:36:01下载
- 积分：1
