sender的verilog 利用fpga实现-sender using the Verilog FPGA realize

I2C总线芯片AT24C02程序设计 C++编程(I2C bus AT24C02 chip program design)

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

六十进制计数器用于计数等操作，代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)

控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)

基于FPGA，利用vhdl语言结合matlab工具实现dds,已经仿真(Based on FPGA, VHDL language with matlab tools to achieve DDS, has simulation)

ＡＤ转换代码，主要练习，没有具体的功能可以实现的，因为只是一部分(AD conversion code, practice, no specific function can be realized, because only part)

I2C的VHDL源码，从机模式，编译通过。-I2C the VHDL source code, from the mode, the compiler through.

多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)